The present invention relates to a semiconductor device layout method and, in particular, to a layout method for arranging a given number of cells with regularity. Each of the cells includes one or more transistors and one or more passive elements which are wired and connected in a given manner so as to perform a logical operation, and is generally called a functional cell.
In the general data path layout, a plurality of functional cells are arranged with regularity and connected to the wiring in the form of data signal lines and control signal lines. For determining an arrangement of these functional cells, there have been available the following first to fourth layout methods, which will also be described later in further detail with reference to the drawings:
In the first layout method, a cell rank length limiting value is used for limiting a cell rank length, that is, the sum of widths of the functional cells included in one rank. The functional cells are grouped so as to be disposed within the cell rank length limiting value. In each of the groups, the arranging order of the functional cells in the cell rank is determined considering a connecting relationship of the functional cells. Specifically, positional changes of the functional cells are performed as needed to minimize the number of wires between the functional cells.
However, in the foregoing first layout method, when the cell rank limiting value is exceeded upon grouping, it is possible that a functional cell which should be arranged in the present cell rank is arranged in another cell rank. This is caused by the fact that the functional cells are arranged only based on the cell length, that is, without considering a circuit structure. Further, due to the arranging order of the functional cells in one rank, more wiring may be needed, thereby increasing a size of a wiring region.
In the second layout method, each of the functional cells corresponding to each of the ranks is assigned parameters in the form of a group name representing the same group and relative position coordinates representing a relative position of the cell in the group. First, grouping of the functional cells is performed based on the group names, and then the functional cells are disposed per group depending on the relative position coordinates.
In the third layout method, a cell arranging table having relative positions of the functional cells is prepared. Then, with reference to the cell arranging table, the functional cells are arranged using instance names assigned thereto and defined by names representing relative positions of the cells to the groups.
However, in either of the second and third layout methods, since the arrangement of the functional cells is manually given in advance, much labor is required. Further, when arranging the functional cells using the instance names thereof, the arranging operation cannot but rely on the form of the instance names.
In the fourth layout method, as described in Japanese First (unexamined) Patent Publication No. 5-152439, the functional cells are arranged in a direction of propagation of the data signals, and the control signals and the data signals are delivered through the first layer metal wiring and the second layer metal wiring, respectively, so as to achieve the high-density layout.
However, in the fourth layout method, it is possible that the first layer metal wiring and the second layer metal wiring are not arranged linearly so that the size of the wiring region is increased.